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Espressif Systems /ESP32-S2 /SPI0 /SLAVE1

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Interpret as SLAVE1

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (SLV_ADDR_ERR_CLR)SLV_ADDR_ERR_CLR 0 (SLV_CMD_ERR_CLR)SLV_CMD_ERR_CLR 0 (SLV_NO_QPI_EN)SLV_NO_QPI_EN 0 (SLV_ADDR_ERR)SLV_ADDR_ERR 0 (SLV_CMD_ERR)SLV_CMD_ERR 0 (SLV_WR_DMA_DONE)SLV_WR_DMA_DONE 0SLV_LAST_COMMAND0SLV_LAST_ADDR

Description

SPI slave control register 1

Fields

SLV_ADDR_ERR_CLR

1: Clear SPI_SLV_ADDR_ERR. 0: not valid. Can be changed by CONF_buf.
SLV_CMD_ERR_CLR

1: Clear SPI_SLV_CMD_ERR. 0: not valid. Can be changed by CONF_buf.
SLV_NO_QPI_EN

1: spi slave QPI mode is not supported. 0: spi slave QPI mode is supported.
SLV_ADDR_ERR

1: The address value of the last SPI transfer is not supported by SPI slave. 0: The address value is supported or no address value is received.
SLV_CMD_ERR

1: The command value of the last SPI transfer is not supported by SPI slave. 0: The command value is supported or no command value is received.
SLV_WR_DMA_DONE

The interrupt raw bit for the completion of dma write operation in the slave mode. Can not be changed by CONF_buf.
SLV_LAST_COMMAND

In the slave mode it is the value of command.
SLV_LAST_ADDR

In the slave mode it is the value of address.

Links

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Register License

Copyright 2024 Espressif Systems (Shanghai) PTE LTD

Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data